A fast logic mapping algorithm for multiple-type-defect tolerance in reconfigurable nano-crossbar arrays

IEEE Transactions on Emerging Topics in Computing ( Early Access Journal article )Unlike conventional CMOS circuits, nano-crossbar arrays have considerably high defect rates. Multiple-type defects randomly occur both on crosspoint switches and wires that substantially complicates the design phase of the circuits with an elimination of systematic design choices. In order to overcome this problem, a logic mapping methodology is presented in this paper. A fast heuristic algorithm using pre-mapping logic morphing, defect oriented adaptive sorting, matching with Hadamard multiplication, and backtracking is introduced. The proposed algorithm covers both crosspoint defects including stuck-open and stuck-closed types and wire defects including bridging and broken types. Effects of stuck-closed defects, mostly disregarded in the literature, are studied in depth. In simulations, an industrial benchmark suit is used for obtaining runtime and success rate values of the proposed algorithm in comparison with those of the existing algorithms in the literature. A relative accuracy evaluation is also given in comparison with exact mapping techniques. Finally, the steps of the algorithm that are based on pre-mapping and heuristic matching techniques, are separately justified with experimental results.This work is supported by the EU-H2020-RISE project NANOxCOMP #691178 and the TUBITAK-Career project #113E760.Early access versio

Permanent and transient fault tolerance for reconfigurable nano-crossbar arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm's effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer project is supported by the EU-H2020-RISE project NANOxCOMP 691178 and the TUBITAK-CAREER project 113E760.Accepted for publicatio

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions

This is a conference paper.During the fabrication of nano-crossbar arrays, certain amount of defective elements are introduced to the end product which affect the yield drastically. Current literature regarding the yield analysis of nano-crossbar arrays is very rough and limited to the uniform distribution of defect occurrence with a few exceptions. Since density feature of crossbar architectures is the main attracting point, we perform a detailed yield analysis by considering both uniform and non-uniform defect distributions. Firstly, we briefly explain the present algorithms and their features used in defect tolerant logic mapping. Secondly, we explain different defect distributions and logic function assumptions used in the literature. Thirdly, we formalize an approximate successful mapping probability metric for uniform distributions and determine area overheads. After that, we apply a regional defect density analysis by comparing uniform and clustered defects to formulate a looser upper bound for area overheads regarding clustered distributions. Finally, we conduct extensive experimental simulations with different defect distributions.This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178. This work is supported by the TUBITAK-Career project #113E760.Accepted versio

Permanent and transient fault tolerance for reconfigurable nano-crossbar arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm's effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer project is supported by the EU-H2020-RISE project NANOxCOMP 691178 and the TUBITAK-CAREER project 113E760.Accepted for publicatio

Logic synthesis and defect tolerance for memristive crossbar arrays

This is a conference paper.Contrary to abundant memory related studies of memristive crossbar structures, logic oriented applications are only gaining popularity in recent years. In this paper, we study logic synthesis, regarding both two-level and multi level designs, and defect aspects of memristor based crossbar architectures. First, we introduce our two-level and multi-level logic synthesis techniques. We elaborate on advantages and disadvantages of both approaches with experimental results regarding area cost. After that, we devise a defect model in alignment with the conventional stuck-at open and closed paradigm. In addition, we determine the effects of defects to the operational capacity of the crossbar. Furthermore, we propose a preliminary defect tolerant Boolean logic mapping approach. In order to evaluate our approach, we conduct extensive Monte Carlo simulations with industrial benchmarks. Finally, we discuss future directions concerning both existing two-level and prospective multi-level logic designs as well as defect tolerance with area redundancy.This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skodowska-Curie grant agreement No 691178. This work is supported by the TUBITAK-Career project #113E760.Publishe

Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

In this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E76

Integrated Synthesis Methodology for Crossbar Arrays

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E76

An adaptive genetic algorithm approach for the mixed-model assembly line sequencing problem

A mixed-model assembly line (MMAL) is a type of production line that is capable of producing a variety of different product models simultaneously and continuously. The design and planning of such lines involve several long- and short-term problems. Among these problems, determining the sequence of products to be produced has received considerable attention from researchers. This problem is known as the Mixed-Model Assembly Line Sequencing Problem (MMALSP). This paper proposes an adaptive genetic algorithm approach to solve MMALSP where multiple objectives such as variation in part consumption rates, total utility work and setup costs are considered simultaneously. The proposed approach integrates an adaptive parameter control (APC) mechanism into a multi-objective genetic algorithm in order to improve the exploration and exploitation capabilities of the algorithm. The APC mechanism decides the probability of mutation and the elites that will be preserved for succeeding generations, all based on the feedback obtained during the run of the algorithm. Experimental results show that the proposed adaptive GA-based approach outperforms the non-adaptive algorithm in both solution quantity and quality